1. Field of the Invention
The present invention relates to a semiconductor memory device having memory cells each composed of a capacitor for accumulating an electric charge and a transistor for charging and discharging said capacitor, and a process for producing said memory device.
2. Related Background Art
Semiconductor memories can be roughly classified into read-only memories and random access memories. In the following there will be explained the vertical structure of a MOS dynamic memory (DRAM) as a representative example of the semiconductor memories.
FIG. 1 is a vertical cross-sectional view of a DRAM wherein, in a silicon substrate 1, a diffusion layer 2 is formed to constitute a bit line or a drain. A first polysilicon electrode 3 constitutes a capacitor electrode. An aluminum electrode 6, constituting a word line, contacts a second polysilicon electrode 4 which is connected to the gate 7 of a MOS transistor. Two polysilicon electrodes are insulated by an oxide layer 5. A source diffusion layer is not provided, but an inversion layer below the two polysilicon electrodes serves as the source domain and the other electrode of the capacitor.
FIG. 2 is a circuit diagram of one bit of the above-explained DRAM, wherein same components as those in FIG. 1 are represented by same numbers.
In the circuit shown in FIG. 2, the readout voltage VD is represented by: EQU VD=VS.times.CS/(CS+CD)
wherein CD is the parasite capacitance 8 of the bit line 2, CS is the capacitance of the capacitor 9, and VS is the voltage accumulated in said capacitor 9. Thus the readout voltage VD decreases with the increase in the memory capacity, due to the increase in the capacitance of the bit line. As the performance of the sense amplifier and the fine geometry patterning with the photolithographic process are now approaching limit, it is necessary to increase the capacitance of the capacitor 9 or to reduce the parasite capacitance 8, in order to obtain a same output voltage while increasing the capacity of the memory.
In the former method it has been proposed to increase the capacitance per unit area through the use of a trench capacitor.
On the other hand, in the latter method, there has been proposed the use of a SOS (silicon-on-sapphire) structure.
However a memory employing such trench capacitor requires a complex manufacturing process, due to the presence of steps required for forming said trench.
Also the SOS structure has been associated with drawbacks that the monocystalline silicon layer formed on sapphire shows lattice defects due to the difference in lattice constant of the two, and that the leak current of the memory is influenced unfavorably due to diffusion of aluminum, which a component of sapphire, into the thin silicon layer.